In digital electronic systems it is important to provide rapid communication between the different modules as the signal delays incurred in such communication can have a significantly adverse effect on the performance of the system. As systems become larger and more complex there is an increase in the number of modules connected to a bus conveying data or other signals from one module to another, with a consequent increase in the loading, usually capacitive, on the bus. In order to prevent the response time of the bus becoming lengthened unacceptably by the increased loading, the power outputs from the modules driving the bus need to be increased. The modules themselves are usually in integrated circuit form and the search for an increase in their speed of operation has led to their being made smaller. That reduction in size has meant a corresponding reduction in the loading on the buses to which the modules are connected, but the increase in speed that would be expected to result from the reduction in loading is not achieved, or is achieved only in part, because the reduction in size has also meant a reduction in the ability of the modules to drive the buses at the speeds required because of their smaller power outputs. That difficulty remains when the modules and the buses are all in the same integrated circuit.
It is an object of the present invention to overcome the above difficulty at least partially.